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SubjectRe: [PATCH v3 10/12] watchdog: s3c2410: Support separate source clock
On 07/11/2021 21:29, Sam Protsenko wrote:
> Right now all devices supported in the driver have the single clock: it
> acts simultaneously as a bus clock (providing register interface
> clocking) and source clock (driving watchdog counter). Some newer Exynos
> chips, like Exynos850, have two separate clocks for that. In that case
> two clocks will be passed to the driver from the resource provider, e.g.
> Device Tree. Provide necessary infrastructure to support that case:
> - use source clock's rate for all timer related calculations
> - use bus clock to gate/ungate the register interface
> All devices that use the single clock are kept intact: if only one clock
> is passed from Device Tree, it will be used for both purposes as before.
> Signed-off-by: Sam Protsenko <>
> ---
> Changes in v3:
> - Removed has_src_clk field: clk framework can handle NULL clk; added
> s3c2410wdt_get_freq() function instead, to figure out which clock to
> use for getting the rate
> Changes in v2:
> - Reworded commit message to be more formal
> - Used separate "has_src_clk" trait to tell if source clock is present
> - Renamed clock variables to match their purpose
> - Removed caching source clock rate, obtaining it in place each time
> instead
> - Renamed err labels for more consistency
> drivers/watchdog/s3c2410_wdt.c | 56 +++++++++++++++++++++++++---------
> 1 file changed, 41 insertions(+), 15 deletions(-)

Reviewed-by: Krzysztof Kozlowski <>

Best regards,

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