Messages in this thread | | | From | Wei Fu <> | Date | Wed, 1 Dec 2021 10:58:46 +0800 | Subject | Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt |
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Hi Heiko, Thanks for your correction , this was my typo when I did the "sed" to replace the word. I need to make a V5 ASAP
On Wed, Dec 1, 2021 at 2:46 AM Heiko Stübner <heiko@sntech.de> wrote: > > Am Montag, 29. November 2021, 02:40:06 CET schrieb wefu@redhat.com: > > From: Wei Fu <wefu@redhat.com> > > > > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" > > in the DT mmu node. Update dt-bindings related property here. > > > > Signed-off-by: Wei Fu <wefu@redhat.com> > > Co-developed-by: Guo Ren <guoren@kernel.org> > > Signed-off-by: Guo Ren <guoren@kernel.org> > > Cc: Anup Patel <anup@brainfault.org> > > Cc: Palmer Dabbelt <palmer@dabbelt.com> > > Cc: Rob Herring <robh+dt@kernel.org> > > --- > > Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > index aa5fb64d57eb..9ff9cbdd8a85 100644 > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > @@ -63,6 +63,16 @@ properties: > > - riscv,sv48 > > - riscv,none > > > > + mmu: > > + description: > > + Describes the CPU's MMU Standard Extensions support. > > + These values originate from the RISC-V Privileged > > + Specification document, available from > > + https://riscv.org/specifications/ > > + $ref: '/schemas/types.yaml#/definitions/string' > > + enum: > > + - riscv,svpmbt > > shouldn't that be "riscv,svpbmt" ? [the m is at the wrong location it seems] > > > + > > riscv,isa: > > description: > > Identifies the specific RISC-V instruction set architecture > > > > > >
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