Messages in this thread Patch in this message | | | From | wefu@redhat ... | Subject | [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt | Date | Mon, 29 Nov 2021 09:40:06 +0800 |
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From: Wei Fu <wefu@redhat.com>
Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt" in the DT mmu node. Update dt-bindings related property here.
Signed-off-by: Wei Fu <wefu@redhat.com> Co-developed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Guo Ren <guoren@kernel.org> Cc: Anup Patel <anup@brainfault.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Rob Herring <robh+dt@kernel.org> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index aa5fb64d57eb..9ff9cbdd8a85 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -63,6 +63,16 @@ properties: - riscv,sv48 - riscv,none + mmu: + description: + Describes the CPU's MMU Standard Extensions support. + These values originate from the RISC-V Privileged + Specification document, available from + https://riscv.org/specifications/ + $ref: '/schemas/types.yaml#/definitions/string' + enum: + - riscv,svpmbt + riscv,isa: description: Identifies the specific RISC-V instruction set architecture -- 2.25.4
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