Messages in this thread | | | Subject | Re: [PATCH] MIPS: update tlb even if pte entry has no change | From | maobibo <> | Date | Thu, 14 May 2020 19:41:56 +0800 |
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On 05/14/2020 05:37 PM, Sergei Shtylyov wrote: > On 14.05.2020 12:35, Sergei Shtylyov wrote: > >>> From: bibo mao <maobibo@loongson.cn> >>> >>> If there are two threads reading the same memory and tlb miss happens, >>> one thread fills pte entry, the other reads new pte value during page fault >>> handling. PTE value may be updated before page faul, so the process need >> >> Fault. > > And "needs". > >>> need update tlb still. > > Oh, and one "need" is enough. :-)
Thank for reviewing my patch, will fix this typo issue in next version.
Best Regards bibo, mao
> >>> Also this patch define flush_tlb_fix_spurious_fault as empty, since it not >>> necessary to flush the page for all CPUs >>> >>> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >> [...] > > MBR, Sergei
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