Messages in this thread | | | Subject | Re: [PATCH] MIPS: update tlb even if pte entry has no change | From | Sergei Shtylyov <> | Date | Thu, 14 May 2020 12:37:27 +0300 |
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On 14.05.2020 12:35, Sergei Shtylyov wrote:
>> From: bibo mao <maobibo@loongson.cn> >> >> If there are two threads reading the same memory and tlb miss happens, >> one thread fills pte entry, the other reads new pte value during page fault >> handling. PTE value may be updated before page faul, so the process need > > Fault.
And "needs".
>> need update tlb still.
Oh, and one "need" is enough. :-)
>> Also this patch define flush_tlb_fix_spurious_fault as empty, since it not >> necessary to flush the page for all CPUs >> >> Signed-off-by: Bibo Mao <maobibo@loongson.cn> > [...]
MBR, Sergei
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