Messages in this thread Patch in this message | | | From | Matthias Kaehlcke <> | Subject | [PATCH] ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger | Date | Mon, 6 Jan 2020 13:52:13 -0800 |
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The flash write protect pin is currently named 'FW_WP_AP', which is how the signal is called in the schematics. The Chrome OS ABI requires the pin to be named 'AP_FLASH_WP_L', which is also how it is called on all other veyron devices. Rename the pin to match the ABI.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org> ---
arch/arm/boot/dts/rk3288-veyron-fievel.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-veyron-fievel.dts b/arch/arm/boot/dts/rk3288-veyron-fievel.dts index 9a0f55085839d9..d66e720390121d 100644 --- a/arch/arm/boot/dts/rk3288-veyron-fievel.dts +++ b/arch/arm/boot/dts/rk3288-veyron-fievel.dts @@ -382,7 +382,11 @@ &gpio7 { "PWR_LED1", "TPM_INT_H", "SPK_ON", - "FW_WP_AP", + /* + * AP_FLASH_WP_L is Chrome OS ABI. Schematics call + * it FW_WP_AP. + */ + "AP_FLASH_WP_L", "", "CPU_NMI", -- 2.24.1.735.g03f4e72817-goog
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