Messages in this thread | | | From | Jerome Brunet <> | Subject | [PATCH 0/4] clk: meson: fixup g12a mpll | Date | Mon, 25 Mar 2019 12:11:56 +0100 |
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When the g12a support has been initially submitted, the MPLL appeared (overall) fine. At the time, the board I used was falshed with amlogic vendor u-boot. Since then, I moved to an early version on mainline u-boot.
While debugging audio support, I noticed that MPLL based clocks were way above target. It appeared the fractional part of the divider was not working.
To work properly, the MPLLs each needs an initial setting in addition to a common one. No one likes those register sequences but sometimes, like here for PLL clocks, there is no way around it.
The series adds the possibility to set initial register sequence for the ee clock controller and the MPLL driver. It is then used to enable the fractional part of the g12a MPLL.
With this series applied, the fractional part works again but we are still seeing a significant clock jitter (+/- 1,6% for 294912KHz). Discussion are ongoing to explain and, hopefully, solve this as well.
Jerome Brunet (4): clk: meson: mpll: add init callback and regs clk: meson: g12a: add mpll register init sequences clk: meson: eeclk: add init regs clk: meson: g12a: add controller register init
drivers/clk/meson/clk-mpll.c | 33 +++++++++++++++++++++++---------- drivers/clk/meson/clk-mpll.h | 2 ++ drivers/clk/meson/g12a.c | 32 +++++++++++++++++++++++++++++++- drivers/clk/meson/meson-eeclk.c | 3 +++ drivers/clk/meson/meson-eeclk.h | 2 ++ 5 files changed, 61 insertions(+), 11 deletions(-)
-- 2.20.1
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