Messages in this thread Patch in this message | | | From | "Chang S. Bae" <> | Subject | [v3 03/12] x86/fsgsbase/64: Add intrinsics/macros for FSGSBASE instructions | Date | Tue, 23 Oct 2018 11:42:25 -0700 |
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From: Andi Kleen <ak@linux.intel.com>
Add C intrinsics and assembler macros for the new FSBASE and GSBASE instructions.
Very straight forward. Used in followon patches.
[ luto: Rename the variables from FS and GS to FSBASE and GSBASE and make <asm/fsgsbase.h> safe to include on 32-bit kernels. ]
v2: Use __always_inline
[ chang: Revise the changelog. Place them in <asm/fsgsbase.h>. Replace the macros with GAS-compatible ones. ]
If GCC supports it, we can add -mfsgsbase to CFLAGS and use the builtins here for extra performance.
Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@kernel.org> Cc: Dave Hansen <dave.hansen@linux.intel.com> --- arch/x86/include/asm/fsgsbase.h | 72 +++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+)
diff --git a/arch/x86/include/asm/fsgsbase.h b/arch/x86/include/asm/fsgsbase.h index eb377b6e9eed..b4d4509b786c 100644 --- a/arch/x86/include/asm/fsgsbase.h +++ b/arch/x86/include/asm/fsgsbase.h @@ -19,6 +19,44 @@ extern unsigned long x86_gsbase_read_task(struct task_struct *task); extern int x86_fsbase_write_task(struct task_struct *task, unsigned long fsbase); extern int x86_gsbase_write_task(struct task_struct *task, unsigned long gsbase); +/* Must be protected by X86_FEATURE_FSGSBASE check. */ + +static __always_inline unsigned long rdfsbase(void) +{ + unsigned long fsbase; + + asm volatile(".byte 0xf3, 0x48, 0x0f, 0xae, 0xc0 # rdfsbaseq %%rax" + : "=a" (fsbase) + :: "memory"); + + return fsbase; +} + +static __always_inline unsigned long rdgsbase(void) +{ + unsigned long gsbase; + + asm volatile(".byte 0xf3, 0x48, 0x0f, 0xae, 0xc8 # rdgsbaseq %%rax;" + : "=a" (gsbase) + :: "memory"); + + return gsbase; +} + +static __always_inline void wrfsbase(unsigned long fsbase) +{ + asm volatile(".byte 0xf3, 0x48, 0x0f, 0xae, 0xd0 # wrfsbaseq %%rax" + :: "a" (fsbase) + : "memory"); +} + +static __always_inline void wrgsbase(unsigned long gsbase) +{ + asm volatile(".byte 0xf3, 0x48, 0x0f, 0xae, 0xd8 # wrgsbaseq %%rax;" + :: "a" (gsbase) + : "memory"); +} + /* Helper functions for reading/writing FS/GS base */ static inline unsigned long x86_fsbase_read_cpu(void) @@ -44,6 +82,40 @@ extern void x86_gsbase_write_cpu_inactive(unsigned long gsbase); #endif /* CONFIG_X86_64 */ +#else /* __ASSEMBLY__ */ + +#ifdef CONFIG_X86_64 + +#include <asm/inst.h> + +.macro RDGSBASE opd + REG_TYPE rdgsbase_opd_type \opd + .if rdgsbase_opd_type == REG_TYPE_R64 + R64_NUM rdgsbase_opd \opd + .byte 0xf3 + PFX_REX rdgsbase_opd 0 W = 1 + .else + .error "RDGSBASE: only for 64-bit value" + .endif + .byte 0xf, 0xae + MODRM 0xc0 rdgsbase_opd 1 +.endm + +.macro WRGSBASE opd + REG_TYPE wrgsbase_opd_type \opd + .if wrgsbase_opd_type == REG_TYPE_R64 + R64_NUM wrgsbase_opd \opd + .byte 0xf3 + PFX_REX wrgsbase_opd 0 W = 1 + .else + .error "WRGSBASE: only for 64-bit value" + .endif + .byte 0xf, 0xae + MODRM 0xd0 wrgsbase_opd 1 +.endm + +#endif /* CONFIG_X86_64 */ + #endif /* __ASSEMBLY__ */ #endif /* _ASM_FSGSBASE_H */ -- 2.19.1
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