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SubjectRe: [PATCH V2 4/6] x86/MCE/AMD: Introduce deferred error interrupt handler
On Wed, May 06, 2015 at 06:58:56AM -0500, Aravind Gopalakrishnan wrote:
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> index 769f5cd..a7ac1af 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> @@ -12,6 +12,8 @@
> * - added support for AMD Family 0x10 processors
> * May 2012
> * - major scrubbing
> + * May 2015
> + * - add support for deferred error interrupts

I added your name here.

> diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
> index e5952c2..cca1124 100644
> --- a/arch/x86/kernel/irq.c
> +++ b/arch/x86/kernel/irq.c
> @@ -116,6 +116,12 @@ int arch_show_interrupts(struct seq_file *p, int prec)
> seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
> seq_puts(p, " Threshold APIC interrupts\n");
> #endif
> +#ifdef CONFIG_X86_MCE_AMD
> + seq_printf(p, "%*s: ", prec, "DEF");

Changed that to "DFR" as "DEF" looks like DEFAULT.

With that: applied, thanks.

--
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
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