Messages in this thread | | | Date | Fri, 20 Jun 2014 10:00:27 +0200 (CEST) | From | Thomas Gleixner <> | Subject | Re: [patch 09/13] irqchip: spear_shirq: Kill the clear_reg nonsense |
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On Fri, 20 Jun 2014, Viresh Kumar wrote:
> On Fri, Jun 20, 2014 at 3:04 AM, Thomas Gleixner <tglx@linutronix.de> wrote: > > None of the chips has a ACK register. > > I need to recheck on this after looking at datasheets. Arranging for > them, will revert by tomorrow. > > > The code brainlessly fiddles > > with the enable register, so it might even reenable a disabled > > interrupt at least on spear300. > > Ack/Clear register is only configured for SPEAr320, how will it > make a difference to SPEAr300 ?
Sorry, my bad. misread the code. So this wants a different changelog.
> And for SPEAr320 as well, the offset mentioned in code for clear > register is different then ENABLE register.
I still don't see why you'd write something into the status register on 320, which is RO according to documentation.
> > @@ -150,13 +141,6 @@ static struct spear_shirq spear320_shirq > > .nr_irqs = 7, > > .mask = ((0x1 << 7) - 1) << 0, > > .disabled = 1, > > - .regs = { > > - .enb_reg = SPEAR320_INT_ENB_MASK_REG, > > - .reset_to_enb = 1, > > - .status_reg = SPEAR320_INT_STS_MASK_REG, > > - .clear_reg = SPEAR320_INT_CLR_MASK_REG, > > - .reset_to_clear = 1, > > - }, > > Was removing .regs completely intentional? > > I don't see these registers getting added again in later patches.
Yes, because that block is NEVER used because disabled = 1
Thanks,
tglx
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