Messages in this thread | | | From | Chew Chiau Ee <> | Subject | [PATCH 0/2] Add PCI mode support for BayTrail LPSS SPI | Date | Fri, 18 Apr 2014 00:26:05 +0800 |
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From: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Hi,
BayTrail LPSS subsystem consists of one SPI host which can be PCI enumerated. PXA2XX PCI layer used to support only CE4100's SPI. Thus, we convert it into a generic PCI layer to add support for LPSS SPI as well.
Since PCI mode LPSS SPI does not rely on common clock framework, we need a mechanism to pass in the host supported clock rate to core layer. Thus, we introduced a new member known as "max_clk_rate" under struct pxa2xx_spi_master which can be used in PCI glue layer to pass in host supported clock rate info.
Chew, Chiau Ee (2): spi/pxa2xx-pci: Add PCI mode support for BayTrail LPSS SPI spi/pxa2xx-pci: Pass host clock rate info from PCI glue layer
Documentation/spi/pxa2xx | 3 ++ drivers/spi/spi-pxa2xx-pci.c | 79 ++++++++++++++++++++++++++++++++-------- drivers/spi/spi-pxa2xx.c | 2 + include/linux/spi/pxa2xx_spi.h | 1 + 4 files changed, 70 insertions(+), 15 deletions(-)
-- 1.7.4.4
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