Messages in this thread | | | Date | Sat, 4 Mar 2006 21:58:04 +1100 | From | Paul Mackerras <> | Subject | Re: Memory barriers and spin_unlock safety |
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Benjamin Herrenschmidt writes:
> Actually, the ppc's full barrier (sync) will generate bus traffic, and I > think in some case eieio barriers can propagate to the chipset to > enforce ordering there too depending on some voodoo settings and wether > the storage space is cacheable or not.
Eieio has to go to the PCI host bridge because it is supposed to prevent write-combining, both in the host bridge and in the CPU.
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