Messages in this thread | | | Subject | Re: Memory barriers and spin_unlock safety | From | Benjamin Herrenschmidt <> | Date | Sun, 05 Mar 2006 09:49:53 +1100 |
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On Sat, 2006-03-04 at 21:58 +1100, Paul Mackerras wrote: > Benjamin Herrenschmidt writes: > > > Actually, the ppc's full barrier (sync) will generate bus traffic, and I > > think in some case eieio barriers can propagate to the chipset to > > enforce ordering there too depending on some voodoo settings and wether > > the storage space is cacheable or not. > > Eieio has to go to the PCI host bridge because it is supposed to > prevent write-combining, both in the host bridge and in the CPU.
That can be disabled with HID bits tho ;)
Ben.
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