Messages in this thread | | | Date | Sat, 4 Mar 2006 21:58:06 +1100 | From | Paul Mackerras <> | Subject | Re: Memory barriers and spin_unlock safety |
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Linus Torvalds writes:
> PPC has an absolutely _horrible_ memory ordering implementation, as far as > I can tell. The thing is broken. I think it's just implementation > breakage, not anything really fundamental, but the fact that their write > barriers are expensive is a big sign that they are doing something bad.
An smp_wmb() is just an eieio on PPC, which is pretty cheap. I made wmb() be a sync though, because it seemed that there were drivers that expected wmb() to provide an ordering between a write to memory and a write to an MMIO register. If that is a bogus assumption then we could make wmb() lighter-weight (after auditing all the drivers we're interested in, of course, ...).
And in a subsequent message:
> If so, a simple write barrier should be sufficient. That's exactly what > the x86 write barriers do too, ie stores to magic IO space are _not_ > ordered wrt a normal [smp_]wmb() (or, as per how this thread started, a > spin_unlock()) at all.
By magic IO space, do you mean just any old memory-mapped device register in a PCI device, or do you mean something else?
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