Messages in this thread | | | Subject | Re: Dual core Athlons and unsynced TSCs | From | Sven-Thorsten Dietrich <> | Date | Fri, 13 Jan 2006 14:18:18 -0800 |
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On Fri, 2006-01-13 at 14:05 -0800, David Lang wrote: > On Fri, 13 Jan 2006 thockin@hockin.org wrote: > > > On Fri, Jan 13, 2006 at 01:18:35PM -0800, David Lang wrote: > >> Lee, the last time I saw this discussion I thought it was identified that > >> the multiple cores (or IIRC the multiple chips in a SMP motherboard) would > >> only get out of sync when power management calls were made (hlt or > >> switching the c-state). IIRC the workaround that was posted then was to > >> just disable these in the kernel build. > > > > not using 'hlt' when idling means that you spend 10s of Watts more power > > on mostly idle systems. > > true, but for people who need better time accruacy then the other > workaround this may be very acceptable. >
1/4 KW / day for time synchronisation.
The power company would love that.
> David Lang > -- *********************************** Sven-Thorsten Dietrich Real-Time Software Architect MontaVista Software, Inc. 1237 East Arques Ave. Sunnyvale, CA 94085
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