Messages in this thread Patch in this message | | | From | Claudiu <> | Subject | [PATCH 11/17] clk: renesas: r9a09g011: Add initial support for power domains | Date | Thu, 8 Feb 2024 14:42:54 +0200 |
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From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Instantiate always-on power domain for R9A09G011 SoC. At the moment, all the IPs are part of this domain.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> --- drivers/clk/renesas/r9a09g011-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c index dda9f29dff33..9d090075f3be 100644 --- a/drivers/clk/renesas/r9a09g011-cpg.c +++ b/drivers/clk/renesas/r9a09g011-cpg.c @@ -245,6 +245,11 @@ static const unsigned int r9a09g011_crit_mod_clks[] __initconst = { MOD_CLK_BASE + R9A09G011_URT_PCLK, }; +static const struct rzg2l_cpg_pm_domain_init_data r9a09g011_pm_domains[] = { + DEF_PD("always-on", R9A09G011_PD_ALWAYS_ON, 0, 0, + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), +}; + const struct rzg2l_cpg_info r9a09g011_cpg_info = { /* Core Clocks */ .core_clks = r9a09g011_core_clks, @@ -265,5 +270,9 @@ const struct rzg2l_cpg_info r9a09g011_cpg_info = { .resets = r9a09g011_resets, .num_resets = ARRAY_SIZE(r9a09g011_resets), + /* PM domains */ + .pm_domains = r9a09g011_pm_domains, + .num_pm_domains = ARRAY_SIZE(r9a09g011_pm_domains), + .has_clk_mon_regs = false, }; -- 2.39.2
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