Messages in this thread | | | From | weilin.wang@intel ... | Subject | [RFC PATCH v1 0/5] TPEBS counting mode support | Date | Wed, 21 Feb 2024 02:20:54 -0500 |
| |
From: Weilin Wang <weilin.wang@intel.com>
TPEBS is one of the features provided by the next generation of Intel PMU. Please refer to Section 8.4.1 of "Intel® Architecture Instruction Set Extensions Programming Reference" [1] for more details about this feature.
This set of patches supports TPEBS in counting mode. The code works in the following way: it forks a perf record process from perf stat when retire_latency of one or more events are used in a metric formula. Perf stat would send a SIGTERM signal to perf record before it needs the retire latency value for metric calculation. Perf stat will then process sample data to extract the retire latency data for metric calculations. Currently, the code uses the arithmetic average of retire latency values.
[1] https://www.intel.com/content/www/us/en/content-details/812218/intel-architecture-instruction-set-extensions-programming-reference.html?wapkw=future%20features
perf stat: Parse and find tpebs events when parsing metrics to prepare for perf record sampling perf stat: Fork and launch perf record when perf stat needs to get retire latency value for a metric. perf stat: Add retire latency values into the expr_parse_ctx to prepare for final metric calculation perf stat: Create another thread for sample data processing perf stat: Add retire latency print functions to print out at the very end of print out
tools/perf/builtin-stat.c | 222 ++++++++++++++++++++++++++++++++- tools/perf/util/data.c | 4 + tools/perf/util/data.h | 1 + tools/perf/util/metricgroup.c | 61 +++++++-- tools/perf/util/metricgroup.h | 18 ++- tools/perf/util/stat-display.c | 65 ++++++++++ tools/perf/util/stat-shadow.c | 18 +++ tools/perf/util/stat.h | 5 + 8 files changed, 376 insertions(+), 18 deletions(-)
-- 2.43.0
| |