Messages in this thread | | | Date | Fri, 2 Feb 2024 13:30:11 +0100 | From | Borislav Petkov <> | Subject | Re: [patch v5 09/19] x86/cpu: Provide an AMD/HYGON specific topology parser |
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On Tue, Jan 23, 2024 at 01:53:43PM +0100, Thomas Gleixner wrote: > +static bool parse_8000_0008(struct topo_scan *tscan) > +{ > + struct { > + u32 ncores : 8,
Yeah, so there was some confusion what this field actually means. It is documented correctly in the latest APM:
"NT: number of physical threads - 1. The number of threads in the processor is NT+1 (e.g., if NT = 0, then there is one thread). See “Legacy Method” on page 645."
> + __rsvd0 : 4, > + apicidsize : 4, > + perftscsize : 2, > + __rsvd1 : 14; > + } ecx; > + unsigned int sft; > + > + if (tscan->c->extended_cpuid_level < 0x80000008) > + return false; > + > + cpuid_leaf_reg(0x80000008, CPUID_ECX, &ecx); > + > + /* If the APIC ID size is 0, then get the shift value from ecx.ncores */ > + sft = ecx.apicidsize; > + if (!sft) > + sft = get_count_order(ecx.ncores + 1); > + > + topology_set_dom(tscan, TOPO_CORE_DOMAIN, sft, ecx.ncores + 1);
So yeah, this should be TOPO_SMT_DOMAIN.
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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