Messages in this thread Patch in this message | | | From | Robert Richter <> | Subject | [PATCH v2] cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS window | Date | Fri, 16 Feb 2024 17:01:13 +0100 |
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The Linux CXL subsystem is built on the assumption that HPA == SPA. That is, the host physical address (HPA) the HDM decoder registers are programmed with are system physical addresses (SPA).
During HDM decoder setup, the DVSEC CXL range registers (cxl-3.1, 8.1.3.8) are checked if the memory is enabled and the CXL range is in a HPA window that is described in a CFMWS structure of the CXL host bridge (cxl-3.1, 9.18.1.3).
Now, if the HPA is not an SPA, the CXL range does not match a CFMWS window and the CXL memory range will be disabled then. The HDM decoder stops working which causes system memory being disabled and further a system hang during HDM decoder initialization, typically when a CXL enabled kernel boots.
Prevent a system hang and do not disable the HDM decoder if the decoder's CXL range is not found in a CFMWS window.
Note the change only fixes a hardware hang, but does not implement HPA/SPA translation. Support for this can be added in a follow on patch series.
Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/core/pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a0e7ed5ae25f..18616ca873e5 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -478,8 +478,8 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, } if (!allowed) { - cxl_set_mem_enable(cxlds, 0); - info->mem_enabled = 0; + dev_err(dev, "Range register decodes outside platform defined CXL ranges.\n"); + return -ENXIO; } /* -- 2.39.2
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