Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 31 Jan 2024 14:58:57 +0200 | From | "Kirill A. Shutemov" <> | Subject | Re: [PATCH, RESEND] x86/pat: Simplifying the PAT programming protocol |
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On Wed, Jan 24, 2024 at 03:06:50PM +0200, Kirill A. Shutemov wrote: > The programming protocol for the PAT MSR follows the MTRR programming > protocol. However, this protocol is cumbersome and requires disabling > caching (CR0.CD=1), which is not possible on some platforms. > > Specifically, a TDX guest is not allowed to set CR0.CD. It triggers > a #VE exception. > > Turned out the requirement to follow the MTRR programming protocol for > PAT programming is unnecessarily strict. The new Intel Software > Developer Manual[1] (December 2023) relaxes this requirement. Please > refer to the section titled "Programming the PAT" for more information. > > The AMD documentation does not link PAT programming to MTRR. > > The kernel only needs to flush the TLB after updating the PAT MSR. The > set_memory code already takes care of flushing the TLB and cache when > changing the memory type of a page. > > [1] http://www.intel.com/sdm > > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> > Reviewed-by: Juergen Gross <jgross@suse.com>
Any feedback?
-- Kiryl Shutsemau / Kirill A. Shutemov
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