Messages in this thread Patch in this message | | | From | Yong-Xuan Wang <> | Subject | [PATCH v2 2/3] dt-bindings: riscv: Add Svadu Entry | Date | Fri, 22 Sep 2023 08:56:48 +0000 |
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Add an entry for the Svadu extension to the riscv,isa-extensions property.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index cc1f546fdbdc..b5a0aed0165b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -147,6 +147,12 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware updating + of PTE A/D bits as frozen at commit b65e07c ("move to Frozen + state") of riscv-svadu. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grained -- 2.17.1
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