Messages in this thread | | | Date | Fri, 15 Sep 2023 07:04:56 -0700 | Subject | Re: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology() | From | Arjan van de Ven <> |
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On 9/15/2023 4:54 AM, Peter Zijlstra wrote: > On Tue, Aug 29, 2023 at 08:46:14AM +0530, K Prateek Nayak wrote: >> Hello Arjan, >> >> On 8/28/2023 8:04 PM, Arjan van de Ven wrote: >>> On 8/28/2023 7:28 AM, K Prateek Nayak wrote: >>>>> - Are these really different between AMD and Intel or is this some >>>>> naming convention issue which needs to be resolved? >>>> They do have different characteristics since, on Sapphire >>>> Rapids, the LLC is at a socket boundary despite having multiple >>>> tiles. (Please correct me if I'm wrong, I'm going off of >>>> llc_id shared in this report by Qiuxu Zhuo - >>>> https://lore.kernel.org/all/20230809161219.83084-1-qiuxu.zhuo@intel.com/) >>>> >>> >>> Sapphire reports itself as 1 tile though (since logically it is) as far as I know >>> >> >> I believe there are some variants with multiple tiles, at least the >> following press-release suggests that: >> >> https://www.intc.com/news-events/press-releases/detail/1598/intel-launches-4th-gen-xeon-scalable-processors-max-series >> >> specifically "... combining up to four Intel 7-built tiles on a single >> package, connected using Intel EMIB ...". Perhaps the one from Qiuxu >> Zhuo's report does not contain multiple tiles. > > I think what Arjan was saying that despite them being build using > multipe physical tiles, they describe themselves, in the topology leave, > as being a single tile.
and more than that -- from a software perspective, they truely act as if they are 1 tile (you can do SNC to break that sort of but that's not default and has its own list of downsides)
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