Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology() | Date | Tue, 19 Sep 2023 10:13:39 +0200 |
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On Tue, Sep 19 2023 at 09:24, K Prateek Nayak wrote: > If possible, can you please elaborate on the "software perspective". Say > CPUID leaf 0x1f reports multiple tile, would the data access latency or > cache to cache latency see a noticeable difference? > > I would like to understand what the characteristics of a "Tile" are and > whether they are similar to AMD's CCX instances discoverable by AMD's > extended CPUID leaf 0x80000026. That way, in future, when the generic > topology is used by other subsystems, the data from "TOPO_TILE_DOMAIN" > can be used generically for both Intel and AMD.
I'm not convinced that this is possible. The meaning of these elements is unfortunately not cast in stone, so the association of e.g. cache boundaries is not necessarily static accross a larger range of CPU generations..
We really need to differentiate performance characteristic, hardware feature scope, power management scope etc. and create abstractions which are actually useful for kernel facilities and user space.
From a performance perspective it's irrelevant whether the scope is TILE or whatever. The information needed is the hierarchy, the performance characteristics of a segment in the hierarchy and the costs for cross segment access and cross segment migration.
For hardware features like perf the information needed is what the scope of a particular resource is. Again it's not necessarily useful to know what particular domain type it is.
Powermanagement does not care about the particual type either. It needs to know which scopes affect c-states, clock speeds ... to give the scheduler informtion of how to steer workloads in the most efficient way.
Thanks,
tglx
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