Messages in this thread | | | Date | Fri, 15 Sep 2023 15:44:02 +0300 | Subject | Re: [PATCH v2] i2c: designware: Fix corrupted memory seen in the ISR | From | Jarkko Nikula <> |
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On 9/14/23 02:29, Jan Bottorff wrote: > Errors were happening in the ISR that looked like corrupted > memory. This was because memory writes from the core enabling > interrupts were not yet visible to the core running the ISR. The > kernel log would get the message "i2c_designware APMC0D0F:00: > controller timed out" during in-band IPMI SSIF stress tests. > > Add a write barrier before enabling interrupts to assure data written > by the current core is visible to all cores before the interrupt fires. > > The ARM Barrier Litmus Tests and Cookbook has an example under > Sending Interrupts and Barriers that matches the usage in this > driver. That document says a DSB barrier is required. > > Signed-off-by: Jan Bottorff <janb@os.amperecomputing.com> > Reviewed-by: Yann Sionneau <ysionneau@kalrayinc.com> > Tested-by: Yann Sionneau <ysionneau@kalrayinc.com> > --- > drivers/i2c/busses/i2c-designware-master.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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