Messages in this thread Patch in this message | | | From | Wang Chen <> | Subject | [PATCH 06/12] dt-bindings: timer: Add Sophgo sg2042 clint | Date | Fri, 15 Sep 2023 15:24:15 +0800 |
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From: Inochi Amaoto <inochiama@outlook.com>
The timer and ipi(mswi) of sg2042 are on different addresses. With the same compatible string, this will cause a mismatch when is processed by SBI.
Add two new compatible string formatted like `C9xx-clint-xxx` to identify the timer and ipi device separately, and do not allow c900-clint as the fallback to avoid conflict.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com> --- .../bindings/timer/sifive,clint.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a0185e15a42f..2a86b80c3f1e 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -39,6 +39,14 @@ properties: - allwinner,sun20i-d1-clint - thead,th1520-clint - const: thead,c900-clint + - items: + - enum: + - sophgo,sg2042-clint-mtimer + - const: thead,c900-clint-mtimer + - items: + - enum: + - sophgo,sg2042-clint-mswi + - const: thead,c900-clint-mswi - items: - const: sifive,clint0 - const: riscv,clint0 @@ -74,4 +82,22 @@ examples: <&cpu4intc 3>, <&cpu4intc 7>; reg = <0x2000000 0x10000>; }; + - | + clint-mtimer@ac010000 { + compatible = "sophgo,sg2042-clint-mtimer", "thead,c900-clint-mtimer"; + interrupts-extended = <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg = <0xac010000 0x00007ff8>; + }; + - | + clint-mswi@94000000 { + compatible = "sophgo,sg2042-clint-mswi", "thead,c900-clint-mswi"; + interrupts-extended = <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg = <0x94000000 0x00004000>; + }; ... -- 2.25.1
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