Messages in this thread | | | Date | Fri, 4 Aug 2023 12:05:32 +0200 | From | Neil Armstrong <> | Subject | Re: [PATCH v7 2/9] clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks |
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On 04/08/2023 11:59, Jerome Brunet wrote: > > On Thu 03 Aug 2023 at 14:03, Neil Armstrong <neil.armstrong@linaro.org> wrote: > >> Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible >> SoCs, they are used to feed the VPU LCD Pixel encoder used for >> DSI display purposes. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> drivers/clk/meson/g12a.c | 40 ++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 40 insertions(+) >> >> diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c >> index ceabd5f4b2ac..5d62134335c1 100644 >> --- a/drivers/clk/meson/g12a.c >> +++ b/drivers/clk/meson/g12a.c >> @@ -3549,6 +3549,22 @@ static struct clk_regmap g12a_cts_encp_sel = { >> }, >> }; >> >> +static struct clk_regmap g12a_cts_encl_sel = { >> + .data = &(struct clk_regmap_mux_data){ >> + .offset = HHI_VIID_CLK_DIV, >> + .mask = 0xf, >> + .shift = 12, >> + .table = mux_table_cts_sel, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "cts_encl_sel", >> + .ops = &clk_regmap_mux_ops, >> + .parent_hws = g12a_cts_parent_hws, >> + .num_parents = ARRAY_SIZE(g12a_cts_parent_hws), >> + .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, > > Why nocache ? > This is usually used when the consumer driver is poking around behind > CCF back. > > Any chance this can use assigned-parent or CCF directly ? > >> + }, >> +}; >> + >> static struct clk_regmap g12a_cts_vdac_sel = { >> .data = &(struct clk_regmap_mux_data){ >> .offset = HHI_VIID_CLK_DIV, >> @@ -3628,6 +3644,22 @@ static struct clk_regmap g12a_cts_encp = { >> }, >> }; >> >> +static struct clk_regmap g12a_cts_encl = { >> + .data = &(struct clk_regmap_gate_data){ >> + .offset = HHI_VID_CLK_CNTL2, >> + .bit_idx = 3, >> + }, >> + .hw.init = &(struct clk_init_data) { >> + .name = "cts_encl", >> + .ops = &clk_regmap_gate_ops, >> + .parent_hws = (const struct clk_hw *[]) { >> + &g12a_cts_encl_sel.hw >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, > > What is the reason for IGNORE_UNUSED ? > If you need to keep the clock on while the driver comes up, please > document it here.
The clocks are added like other video clock, unused & nocache, then enabled correctly in patch 4 to be used by CCF.
Neil
> >> + }, >> +}; >> + >> static struct clk_regmap g12a_cts_vdac = { >> .data = &(struct clk_regmap_gate_data){ >> .offset = HHI_VID_CLK_CNTL2, >> @@ -4407,10 +4439,12 @@ static struct clk_hw *g12a_hw_clks[] = { >> [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, >> [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, >> [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, >> + [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, >> [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, >> [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, >> [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, >> [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, >> + [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, >> [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, >> [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, >> [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, >> @@ -4632,10 +4666,12 @@ static struct clk_hw *g12b_hw_clks[] = { >> [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, >> [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, >> [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, >> + [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, >> [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, >> [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, >> [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, >> [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, >> + [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, >> [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, >> [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, >> [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, >> @@ -4892,10 +4928,12 @@ static struct clk_hw *sm1_hw_clks[] = { >> [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, >> [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, >> [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, >> + [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, >> [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, >> [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, >> [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, >> [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, >> + [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, >> [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, >> [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, >> [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, >> @@ -5123,10 +5161,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = { >> &g12a_vclk2_div12_en, >> &g12a_cts_enci_sel, >> &g12a_cts_encp_sel, >> + &g12a_cts_encl_sel, >> &g12a_cts_vdac_sel, >> &g12a_hdmi_tx_sel, >> &g12a_cts_enci, >> &g12a_cts_encp, >> + &g12a_cts_encl, >> &g12a_cts_vdac, >> &g12a_hdmi_tx, >> &g12a_hdmi_sel, >
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