Messages in this thread Patch in this message | | | From | Ilkka Koskinen <> | Subject | [PATCH v6 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes | Date | Mon, 14 Aug 2023 23:35:23 -0700 |
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Split the 64-bit register accesses if 64-bit access is not supported by the PMU.
Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com> --- drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c index 04be94b4aa48..6387cbad7a7d 100644 --- a/drivers/perf/arm_cspmu/arm_cspmu.c +++ b/drivers/perf/arm_cspmu/arm_cspmu.c @@ -715,7 +715,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val) if (use_64b_counter_reg(cspmu)) { offset = counter_offset(sizeof(u64), event->hw.idx); - writeq(val, cspmu->base1 + offset); + if (cspmu->has_atomic_dword) + writeq(val, cspmu->base1 + offset); + else + lo_hi_writeq(val, cspmu->base1 + offset); } else { offset = counter_offset(sizeof(u32), event->hw.idx); -- 2.41.0
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