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SubjectRe: [PATCH v6 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
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On 15/08/2023 07:35, Ilkka Koskinen wrote:
> Split the 64-bit register accesses if 64-bit access is not supported
> by the PMU.
>
> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>
> Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>

Do we need a Fixes tag ?

With that:

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Suzuki

> ---
> drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
> index 04be94b4aa48..6387cbad7a7d 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
> @@ -715,7 +715,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
> if (use_64b_counter_reg(cspmu)) {
> offset = counter_offset(sizeof(u64), event->hw.idx);
>
> - writeq(val, cspmu->base1 + offset);
> + if (cspmu->has_atomic_dword)
> + writeq(val, cspmu->base1 + offset);
> + else
> + lo_hi_writeq(val, cspmu->base1 + offset);


> } else {
> offset = counter_offset(sizeof(u32), event->hw.idx);
>

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