Messages in this thread | | | Date | Tue, 4 Jul 2023 11:01:32 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH] x86/barrier: Do not serialize MSR accesses on AMD |
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On Tue, Jul 04, 2023 at 09:46:31AM +0200, Borislav Petkov wrote: > On Mon, Jul 03, 2023 at 02:54:19PM +0200, Peter Zijlstra wrote: > > So you're saying that AMD tsc_deadline and x2apic MSRs *do* imply > > ordering constraints unlike the Intel ones? > > Yah, that's the default situation. Only those two - TSC_DEADLINE and > x2APIC MSRs - and on *Intel* are special.
So they are normal MSRs like all other? AMD doesn't have any exceptions for MSRs, they all the same?
> > Both instructions are 3 bytes, a 6 byte nop would be better, no? > > Why? You wanna save the branch insn when sending IPIs through the > x2APIC? Does that really matter? I doubt it...
Dunno, code density, speculation, many raisons to avoid jumps :-)
> > asm volatile (ALTERNATIVE("mfence; lfence;", "", X86_FEATURE_AMD)); > > There's no X86_FEATURE_AMD :)
I know, but that's easily fixed.
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