Messages in this thread | ![/](/images/icornerl.gif) | | Date | Tue, 4 Jul 2023 09:46:31 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH] x86/barrier: Do not serialize MSR accesses on AMD |
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On Mon, Jul 03, 2023 at 02:54:19PM +0200, Peter Zijlstra wrote: > So you're saying that AMD tsc_deadline and x2apic MSRs *do* imply > ordering constraints unlike the Intel ones?
Yah, that's the default situation. Only those two - TSC_DEADLINE and x2APIC MSRs - and on *Intel* are special.
> Can we pls haz a document link for that, also a comment?
Why document the default? The SDM is already documenting this exception. For everything else WRMSR is serializing.
> Moving this code while changing it meant I had to look at it _3_ times > before I spotted you changed it :/
I figured it is a simple enough patch - no need to do a sole movement one.
> Both instructions are 3 bytes, a 6 byte nop would be better, no?
Why? You wanna save the branch insn when sending IPIs through the x2APIC? Does that really matter? I doubt it...
> asm volatile (ALTERNATIVE("mfence; lfence;", "", X86_FEATURE_AMD));
There's no X86_FEATURE_AMD :)
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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