Messages in this thread Patch in this message | | | From | Ante Knezic <> | Subject | [PATCH net-next v3] net: dsa: mv88e6xxx: Add erratum 3.14 for 88E6390X and 88E6190X | Date | Fri, 21 Jul 2023 12:26:18 +0200 |
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Fixes XAUI/RXAUI lane alignment errors. Issue causes dropped packets when trying to communicate over fiber via SERDES lanes of port 9 and 10. Errata document applies only to 88E6190X and 88E6390X devices. Requires poking in undocumented registers.
Signed-off-by: Ante Knezic <ante.knezic@helmholz.de> --- V3 : Rework to fit the new phylink_pcs infrastructure V2 : Rework as suggested by Andrew Lunn <andrew@lun.ch> * make int lanes[] const * reorder prod_nums * update commit message to indicate we are dealing with undocumented Marvell registers and magic values --- drivers/net/dsa/mv88e6xxx/pcs-639x.c | 42 ++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
diff --git a/drivers/net/dsa/mv88e6xxx/pcs-639x.c b/drivers/net/dsa/mv88e6xxx/pcs-639x.c index 98dd49dac421..50b14804c360 100644 --- a/drivers/net/dsa/mv88e6xxx/pcs-639x.c +++ b/drivers/net/dsa/mv88e6xxx/pcs-639x.c @@ -20,6 +20,7 @@ struct mv88e639x_pcs { struct mdio_device mdio; struct phylink_pcs sgmii_pcs; struct phylink_pcs xg_pcs; + struct mv88e6xxx_chip *chip; bool supports_5g; phy_interface_t interface; unsigned int irq; @@ -205,13 +206,52 @@ static void mv88e639x_sgmii_pcs_pre_config(struct phylink_pcs *pcs, mv88e639x_sgmii_pcs_control_pwr(mpcs, false); } +static int mv88e6390_erratum_3_14(struct mv88e639x_pcs *mpcs) +{ + const int lanes[] = { MV88E6390_PORT9_LANE0, MV88E6390_PORT9_LANE1, + MV88E6390_PORT9_LANE2, MV88E6390_PORT9_LANE3, + MV88E6390_PORT10_LANE0, MV88E6390_PORT10_LANE1, + MV88E6390_PORT10_LANE2, MV88E6390_PORT10_LANE3 }; + struct mdio_device mdio; + int err, i; + + /* 88e6190x and 88e6390x errata 3.14: + * After chip reset, SERDES reconfiguration or SERDES core + * Software Reset, the SERDES lanes may not be properly aligned + * resulting in CRC errors + */ + + mdio.bus = mpcs->mdio.bus; + + for (i = 0; i < ARRAY_SIZE(lanes); i++) { + mdio.addr = lanes[i]; + + err = mdiodev_c45_write(&mdio, MDIO_MMD_PHYXS, + 0xf054, 0x400C); + if (err) + return err; + + err = mdiodev_c45_write(&mdio, MDIO_MMD_PHYXS, + 0xf054, 0x4000); + if (err) + return err; + } + + return 0; +} + static int mv88e639x_sgmii_pcs_post_config(struct phylink_pcs *pcs, phy_interface_t interface) { struct mv88e639x_pcs *mpcs = sgmii_pcs_to_mv88e639x_pcs(pcs); + struct mv88e6xxx_chip *chip = mpcs->chip; mv88e639x_sgmii_pcs_control_pwr(mpcs, true); + if (chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6190X || + chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6390X) + mv88e6390_erratum_3_14(mpcs); + return 0; } @@ -523,6 +563,7 @@ static int mv88e6390_pcs_init(struct mv88e6xxx_chip *chip, int port) mpcs->sgmii_pcs.neg_mode = true; mpcs->xg_pcs.ops = &mv88e6390_xg_pcs_ops; mpcs->xg_pcs.neg_mode = true; + mpcs->chip = chip; err = mv88e639x_pcs_setup_irq(mpcs, chip, port); if (err) @@ -873,6 +914,7 @@ static int mv88e6393x_pcs_init(struct mv88e6xxx_chip *chip, int port) mpcs->xg_pcs.ops = &mv88e6393x_xg_pcs_ops; mpcs->xg_pcs.neg_mode = true; mpcs->supports_5g = true; + mpcs->chip = chip; err = mv88e6393x_erratum_4_6(mpcs); if (err) -- 2.11.0
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