Messages in this thread | | | Date | Fri, 14 Jul 2023 12:16:07 +0530 | Subject | Re: [PATCH v3] PCI: j721e: Delay 100ms T_PVPERL from power stable to PERST# inactive | From | "Verma, Achal" <> |
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On 7/7/2023 3:21 PM, Achal Verma wrote: > As per the PCIe Card Electromechanical specification REV. 5.0, PERST# > signal should be de-asserted after minimum 100ms from the time power-rails > become stable. So, to ensure 100ms delay to give sufficient time for > power-rails and refclk to become stable, change delay from 100us to 100ms. > > From PCIe Card Electromechanical specification REV. 5.0 section 2.9.2: > TPVPERL: Power stable to PERST# inactive - 100ms > > Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver") > Signed-off-by: Achal Verma <a-verma1@ti.com> Hello Bjorn,
Could you please bless this with "Reviewed-by" tag.
Thanks, Achal Verma > --- > > Changes from v2: > * Fix commit message. > > Change from v1: > * Add macro for delay value. > > drivers/pci/controller/cadence/pci-j721e.c | 11 +++++------ > drivers/pci/pci.h | 2 ++ > 2 files changed, 7 insertions(+), 6 deletions(-) > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > index e70213c9060a..32b6a7dc3cff 100644 > --- a/drivers/pci/controller/cadence/pci-j721e.c > +++ b/drivers/pci/controller/cadence/pci-j721e.c > @@ -498,14 +498,13 @@ static int j721e_pcie_probe(struct platform_device *pdev) > > /* > * "Power Sequencing and Reset Signal Timings" table in > - * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 > - * indicates PERST# should be deasserted after minimum of 100us > - * once REFCLK is stable. The REFCLK to the connector in RC > - * mode is selected while enabling the PHY. So deassert PERST# > - * after 100 us. > + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 5.0 > + * indicates PERST# should be deasserted after minimum of 100ms > + * after power rails achieve specified operating limits and > + * within this period reference clock should also become stable. > */ > if (gpiod) { > - usleep_range(100, 200); > + msleep(PCIE_TPVPERL_DELAY_MS); > gpiod_set_value_cansleep(gpiod, 1); > } > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index a4c397434057..6ab2367e5867 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -13,6 +13,8 @@ > > #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 > > +#define PCIE_TPVPERL_DELAY_MS 100 /* see PCIe CEM r5.0, sec 2.9.2 */ > + > extern const unsigned char pcie_link_speed[]; > extern bool pci_early_dump; >
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