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Subject[PATCH v2 04/15] dt-bindings: clock: qcom,dispcc-sm6125: Allow power-domains property
On SM6125 the dispcc block is gated behind VDDCX: allow this domain to
be configured.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
index 8fd29915bf2c..9ab8ddad904b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml
@@ -48,6 +48,11 @@ properties:
'#power-domain-cells':
const: 1

+ power-domains:
+ description:
+ A phandle and PM domain specifier for the CX power domain.
+ maxItems: 1
+
reg:
maxItems: 1

@@ -65,6 +70,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@5f00000 {
compatible = "qcom,sm6125-dispcc";
reg = <0x5f00000 0x20000>;
@@ -84,6 +90,7 @@ examples:
"dp_phy_pll_vco_div_clk",
"cfg_ahb_clk",
"gcc_disp_gpll0_div_clk_src";
+ power-domains = <&rpmpd SM6125_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.41.0

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