Messages in this thread | | | Date | Tue, 30 May 2023 13:42:57 -0300 | From | Jason Gunthorpe <> | Subject | Re: [PATCH v3 00/10] Add Intel VT-d nested translation |
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On Mon, May 29, 2023 at 06:16:44PM -0600, Alex Williamson wrote: > On Mon, 29 May 2023 15:43:02 -0300 > Jason Gunthorpe <jgg@nvidia.com> wrote: > > > On Wed, May 24, 2023 at 08:59:43AM +0000, Tian, Kevin wrote: > > > > > At least this looks a reasonable tradeoff to some proprietary VMMs > > > which never adds RO mappings in stage-2 today. > > > > What is the reason for the RO anyhow? > > > > Would it be so bad if it was DMA mapped as RW due to the errata? > > What if it's the zero page? Thanks,
GUP doesn't return the zero page if FOL_WRITE is specified
Jason
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