Messages in this thread | | | Date | Mon, 29 May 2023 18:16:44 -0600 | From | Alex Williamson <> | Subject | Re: [PATCH v3 00/10] Add Intel VT-d nested translation |
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On Mon, 29 May 2023 15:43:02 -0300 Jason Gunthorpe <jgg@nvidia.com> wrote:
> On Wed, May 24, 2023 at 08:59:43AM +0000, Tian, Kevin wrote: > > > At least this looks a reasonable tradeoff to some proprietary VMMs > > which never adds RO mappings in stage-2 today. > > What is the reason for the RO anyhow? > > Would it be so bad if it was DMA mapped as RW due to the errata?
What if it's the zero page? Thanks,
Alex
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