Messages in this thread | | | Date | Tue, 16 May 2023 13:07:29 +0200 | Subject | Re: [PATCH 11/23] arm64: zynqmp: Use assigned-clock-rates for setting up SD clock in SOM | From | Michal Simek <> |
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On 5/2/23 15:35, Michal Simek wrote: > With limited low level configuration done via psu-init only IPs connected > on SOM are initialized and configured. All IPs connected to carrier card > are not initialized. There is a need to do proper reset, pin configuration > and also clock setting. > The patch targets the last part which is setting up proper clock for EMMC > on production SOMs and SD on kv260-revB. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 5 ++++- > arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 + > arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + > arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 1 + > 4 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > index 5e7e1bf5b811..681885c9bcbb 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi > @@ -2,7 +2,8 @@ > /* > * Clock specification for Xilinx ZynqMP > * > - * (C) Copyright 2017 - 2021, Xilinx, Inc. > + * (C) Copyright 2017 - 2022, Xilinx, Inc. > + * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. > * > * Michal Simek <michal.simek@xilinx.com> > */ > @@ -185,10 +186,12 @@ &sata { > > &sdhci0 { > clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>; > + assigned-clocks = <&zynqmp_clk SDIO0_REF>; > }; > > &sdhci1 { > clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>; > + assigned-clocks = <&zynqmp_clk SDIO1_REF>; > }; > > &spi0 { > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso > index 2f7a17ec58b4..cb4a5126c4ec 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso > @@ -133,6 +133,7 @@ &sdhci1 { /* on CC with tuned parameters */ > no-1-8-v; > disable-wp; > xlnx,mio-bank = <1>; > + assigned-clock-rates = <187498123>; > }; > > &gem3 { /* required by spec */ > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso > index 4695e0e3714f..31bc120dee49 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso > @@ -116,6 +116,7 @@ &sdhci1 { /* on CC with tuned parameters */ > clk-phase-sd-hs = <126>, <60>; > clk-phase-uhs-sdr25 = <120>, <60>; > clk-phase-uhs-ddr50 = <126>, <48>; > + assigned-clock-rates = <187498123>; > }; > > &gem3 { /* required by spec */ > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > index 340a5c43a8b6..d3c6a9feb114 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts > @@ -178,6 +178,7 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ > disable-wp; > bus-width = <8>; > xlnx,mio-bank = <0>; > + assigned-clock-rates = <187498123>; > }; > > &spi1 { /* MIO6, 9-11 */
Applied. M
-- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
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