Messages in this thread | | | Date | Fri, 12 May 2023 08:37:11 +0200 | Subject | Re: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node | From | Krzysztof Kozlowski <> |
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On 12/05/2023 04:20, Xingyu Wu wrote: > Add the PLL clock node for the Starfive JH7110 SoC and > modify the SYSCRG node to add PLL clocks input.
> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { > sys_syscon: syscon@13030000 { > compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; > reg = <0x0 0x13030000 0x0 0x1000>; > + > + pllclk: clock-controller { > + compatible = "starfive,jh7110-pll"; > + clocks = <&osc>; > + #clock-cells = <1>;
This should be part of previous patch. You just added that node. Don't add half of devices but entire device.
Best regards, Krzysztof
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