lkml.org 
[lkml]   [2023]   [May]   [12]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    /
    Date
    SubjectRe: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node
    From
    On 2023/5/12 14:37, Krzysztof Kozlowski wrote:
    > On 12/05/2023 04:20, Xingyu Wu wrote:
    >> Add the PLL clock node for the Starfive JH7110 SoC and
    >> modify the SYSCRG node to add PLL clocks input.
    >
    >
    >> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 {
    >> sys_syscon: syscon@13030000 {
    >> compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
    >> reg = <0x0 0x13030000 0x0 0x1000>;
    >> +
    >> + pllclk: clock-controller {
    >> + compatible = "starfive,jh7110-pll";
    >> + clocks = <&osc>;
    >> + #clock-cells = <1>;
    >
    > This should be part of previous patch. You just added that node. Don't
    > add half of devices but entire device.
    >

    So do I merge the patch 6 and patch 7 into one patch and add syscon and
    clock-controller together?

    Best regards,
    Xingyu Wu

    \
     
     \ /
      Last update: 2023-05-12 09:19    [W:2.267 / U:0.024 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site