Messages in this thread | | | From | Konrad Dybcio <> | Subject | [PATCH 0/5] MDSS reg bus interconnect | Date | Mon, 17 Apr 2023 17:30:14 +0200 |
| |
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there's another path that needs to be handled to ensure MDSS functions properly, namely the "reg bus", a.k.a the CPU-MDSS interconnect.
Gating that path may have a variety of effects.. from none to otherwise inexplicable DSI timeouts..
This series tries to address the lack of that.
Example path:
interconnects = <&bimc MASTER_AMPSS_M0 0 &config_noc SLAVE_DISPLAY_CFG 0>;
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Konrad Dybcio (5): dt-bindings: display/msm: Add reg bus interconnect drm/msm/dpu1: Rename path references to mdp_path drm/msm/mdss: Rename path references to mdp_path drm/msm/mdss: Handle the reg bus ICC path drm/msm/dpu1: Handle the reg bus ICC path
.../bindings/display/msm/mdss-common.yaml | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 34 ++++++++++++++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 5 ++-- drivers/gpu/drm/msm/msm_mdss.c | 35 ++++++++++++++-------- 5 files changed, 57 insertions(+), 28 deletions(-) --- base-commit: d3f2cd24819158bb70701c3549e586f9df9cee67 change-id: 20230417-topic-dpu_regbus-abc94a770952
Best regards, -- Konrad Dybcio <konrad.dybcio@linaro.org>
| |