Messages in this thread | | | Date | Thu, 13 Apr 2023 11:06:08 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v3 2/4] cacheinfo: Check cache properties are present in DT |
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On Thu, Apr 13, 2023 at 11:14:32AM +0200, Pierre Gondois wrote: > If a Device Tree (DT) is used, the presence of cache properties is > assumed. Not finding any is not considered. For arm64 platforms, > cache information can be fetched from the clidr_el1 register. > Checking whether cache information is available in the DT > allows to switch to using clidr_el1. > > init_of_cache_level() > \-of_count_cache_leaves() > will assume there a 2 cache leaves (L1 data/instruction caches), which > can be different from clidr_el1 information. > > cache_setup_of_node() tries to read cache properties in the DT. > If there are none, this is considered a success. Knowing no > information was available would allow to switch to using clidr_el1. > > Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count cache leaves") > Reported-by: Alexandre Ghiti <alexghiti@rivosinc.com> > Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/ > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Since there's no longer an error printed Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for the update Pierre, Conor. [unhandled content-type:application/pgp-signature] | |