Messages in this thread | | | Date | Wed, 12 Apr 2023 21:10:30 +0800 | Subject | Re: [PATCH 11/17] iommu/vt-d: Fix operand size in bitwise operation | From | Baolu Lu <> |
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On 2023/4/12 15:11, David Laight wrote: > From: Baolu Lu >> Sent: 12 April 2023 02:32 >> >> On 4/12/23 5:22 AM, David Laight wrote: >>>> Sent: 11 April 2023 07:48 >>>> >>>> From: Tina Zhang<tina.zhang@intel.com> >>>> >>>> The patch fixes the klocwork issues that operands in a bitwise operation >>>> have different size at line 1692 of dmar.c, line 1898 and line 1907 of >>>> iommu.c. >>> Why is this any kind of thing that needs fixing? >> >> This description is a bit misleading. Actually I queued it as a cleanup >> patch. > > Hopefully without 'fix' anywhere in the description. > Otherwise the scripts will pick it for a back-port.
Fair enough.I will refine the commit message like below:
iommu/vt-d: Make size of operands same in bitwise operations
The addresses the following issue reported by klocwork tool:
- operands of different size in bitwise operations
Suggested-by: Yongwei Ma <yongwei.ma@intel.com> Signed-off-by: Tina Zhang <tina.zhang@intel.com>
> >>> - val |= (1 << 11) | 1; >>> + val |= BIT_ULL(11) | BIT_ULL(0); > > More problematic it what is bit 11 anyway?
There is already a comment at the top of the code explaining the meaning of these bits. Because this is not a newly added code, it is not displayed in this patch.
/* * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability * is present. */ if (ecap_smts(iommu->ecap)) val |= BIT_ULL(11) | BIT_ULL(0);
Best regards, baolu
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