Messages in this thread | | | From | Alexandre Ghiti <> | Date | Wed, 12 Apr 2023 11:38:30 +0200 | Subject | Re: [PATCH v2 2/3] cacheinfo: Check cache properties are present in DT |
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Hi Pierre, Conor,
On Wed, Apr 12, 2023 at 10:12 AM Pierre Gondois <pierre.gondois@arm.com> wrote: > > Hello Conor, > > On 4/12/23 09:55, Conor Dooley wrote: > > Hey Pierre! > > > > On Wed, Apr 12, 2023 at 09:18:05AM +0200, Pierre Gondois wrote: > >> If a Device Tree (DT) is used, the presence of cache properties is > >> assumed. Not finding any is not considered. For arm64 platforms, > >> cache information can be fetched from the clidr_el1 register. > >> Checking whether cache information is available in the DT > >> allows to switch to using clidr_el1. > >> > >> init_of_cache_level() > >> \-of_count_cache_leaves() > >> will assume there a 2 cache leaves (L1 data/instruction caches), which > >> can be different from clidr_el1 information. > >> > >> cache_setup_of_node() tries to read cache properties in the DT. > >> If there are none, this is considered a success. Knowing no > >> information was available would allow to switch to using clidr_el1. > > > > Hmm, w/ this series I am still seeing a: > > [ 0.306736] Early cacheinfo failed, ret = -22 > > > > Not finding any cacheinfo is totally valid, right? > > > > A basic RISC-V QEMU setup is sufficient to reproduce, for instance: > > | $(qemu) \ > > | -m 2G -smp 5 \ > > | -M virt -nographic \ > > | -kernel $(vmlinux_bin) > > Sorry I forgot to remove the: > pr_err("Early cacheinfo failed, ret = %d\n", ret);
I have just tested it and the messages "cacheinfo: Unable to detect cache hierarchy for CPU" disappear, I'll add my tested by on the next version. And just to make sure we agree: this fix should go into -fixes (for 6.3).
Thanks again Conor and Pierre,
Alex
> > I ll wait until tomorrow to send a v3 with this fixed. > > Thanks for testing, > Regards, > Pierre > > > > > Cheers, > > Conor. > >
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