Messages in this thread | | | Date | Wed, 12 Apr 2023 08:55:34 +0100 | From | Conor Dooley <> | Subject | Re: [PATCH v2 2/3] cacheinfo: Check cache properties are present in DT |
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Hey Pierre!
On Wed, Apr 12, 2023 at 09:18:05AM +0200, Pierre Gondois wrote: > If a Device Tree (DT) is used, the presence of cache properties is > assumed. Not finding any is not considered. For arm64 platforms, > cache information can be fetched from the clidr_el1 register. > Checking whether cache information is available in the DT > allows to switch to using clidr_el1. > > init_of_cache_level() > \-of_count_cache_leaves() > will assume there a 2 cache leaves (L1 data/instruction caches), which > can be different from clidr_el1 information. > > cache_setup_of_node() tries to read cache properties in the DT. > If there are none, this is considered a success. Knowing no > information was available would allow to switch to using clidr_el1.
Hmm, w/ this series I am still seeing a: [ 0.306736] Early cacheinfo failed, ret = -22
Not finding any cacheinfo is totally valid, right?
A basic RISC-V QEMU setup is sufficient to reproduce, for instance: | $(qemu) \ | -m 2G -smp 5 \ | -M virt -nographic \ | -kernel $(vmlinux_bin)
Cheers, Conor.
> Fixes: de0df442ee49 ("cacheinfo: Check 'cache-unified' property to count cache leaves") > Reported-by: Alexandre Ghiti <alexghiti@rivosinc.com> > Link: https://lore.kernel.org/all/20230404-hatred-swimmer-6fecdf33b57a@spud/ > Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> > --- > drivers/base/cacheinfo.c | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c > index e7ad6aba5f97..6749dc6ebf50 100644 > --- a/drivers/base/cacheinfo.c > +++ b/drivers/base/cacheinfo.c > @@ -78,6 +78,9 @@ bool last_level_cache_is_shared(unsigned int cpu_x, unsigned int cpu_y) > } > > #ifdef CONFIG_OF > + > +static bool of_check_cache_nodes(struct device_node *np); > + > /* OF properties to query for a given cache type */ > struct cache_type_info { > const char *size_prop; > @@ -205,6 +208,11 @@ static int cache_setup_of_node(unsigned int cpu) > return -ENOENT; > } > > + if (!of_check_cache_nodes(np)) { > + of_node_put(np); > + return -ENOENT; > + } > + > prev = np; > > while (index < cache_leaves(cpu)) { > @@ -229,6 +237,25 @@ static int cache_setup_of_node(unsigned int cpu) > return 0; > } > > +static bool of_check_cache_nodes(struct device_node *np) > +{ > + struct device_node *next; > + > + if (of_property_present(np, "cache-size") || > + of_property_present(np, "i-cache-size") || > + of_property_present(np, "d-cache-size") || > + of_property_present(np, "cache-unified")) > + return true; > + > + next = of_find_next_cache_node(np); > + if (next) { > + of_node_put(next); > + return true; > + } > + > + return false; > +} > + > static int of_count_cache_leaves(struct device_node *np) > { > unsigned int leaves = 0; > @@ -260,6 +287,9 @@ int init_of_cache_level(unsigned int cpu) > struct device_node *prev = NULL; > unsigned int levels = 0, leaves, level; > > + if (!of_check_cache_nodes(np)) > + goto err_out; > + > leaves = of_count_cache_leaves(np); > if (leaves > 0) > levels = 1; > -- > 2.25.1 > [unhandled content-type:application/pgp-signature] | |