Messages in this thread | | | From | Roman Beranek <> | Subject | [PATCH 0/3] drm: sun4i: set proper TCON0 DCLK rate in DSI mode | Date | Fri, 31 Mar 2023 13:02:42 +0200 |
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With bpp bits per pixel transmitted over n DSI lanes, the target DCLK rate for a given pixel clock is obtained as follows:
DCLK rate = 1/4 * bpp / n * pixel clock
Effect of this change can be observed through the rate of Vblank IRQs which should now match refresh rate implied by set display mode. It was verified to do so on a A64 board with a 2-lane and a 4-lane panel.
Roman Beranek (3): drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk ARM: dts: sunxi: rename tcon's clock output drm: sun4i: calculate proper DCLK rate for DSI
arch/arm/boot/dts/sun5i.dtsi | 2 +- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +- drivers/gpu/drm/sun4i/Makefile | 2 +- drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 +++++++++++-------- .../{sun4i_dotclock.c => sun4i_tcon_dclk.c} | 2 +- .../{sun4i_dotclock.h => sun4i_tcon_dclk.h} | 0 9 files changed, 33 insertions(+), 27 deletions(-) rename drivers/gpu/drm/sun4i/{sun4i_dotclock.c => sun4i_tcon_dclk.c} (99%) rename drivers/gpu/drm/sun4i/{sun4i_dotclock.h => sun4i_tcon_dclk.h} (100%)
-- 2.32.0 (Apple Git-132)
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