Messages in this thread | | | From | Swapnil Kashinath Jakhade <> | Subject | RE: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration | Date | Mon, 27 Mar 2023 05:34:08 +0000 |
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Hi Vinod,
> -----Original Message----- > From: Roger Quadros <rogerq@kernel.org> > Sent: Monday, February 20, 2023 9:50 PM > To: Swapnil Kashinath Jakhade <sjakhade@cadence.com>; > vkoul@kernel.org; kishon@kernel.org; linux-phy@lists.infradead.org; linux- > kernel@vger.kernel.org > Cc: Milind Parab <mparab@cadence.com> > Subject: Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink > configuration > > EXTERNAL MAIL > > > > > On 20/02/2023 16:12, Swapnil Jakhade wrote: > > Add register sequences for PCIe + SGMII PHY multilink configuration. > > This has been validated on TI J7 platforms. > > > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> > > Reviewed-by: Roger Quadros <rogerq@kernel.org>
Could you please consider reviewing and merging this patch.
Thanks & regards, Swapnil
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