Messages in this thread | | | Date | Mon, 20 Feb 2023 18:20:29 +0200 | Subject | Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration | From | Roger Quadros <> |
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On 20/02/2023 16:12, Swapnil Jakhade wrote: > Add register sequences for PCIe + SGMII PHY multilink configuration. > This has been validated on TI J7 platforms. > > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
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