Messages in this thread Patch in this message | | | From | Florian Fainelli <> | Subject | [PATCH 3/3] memory: brcmstb_memc: Add new DDR attributes | Date | Fri, 24 Mar 2023 09:52:31 -0700 |
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Provide information about the DDR size, type, width, total width, dual/single rank. This is useful for reporting purposes and inventory of the system(s).
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/memory/brcmstb_memc.c | 80 ++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index 67c75e21c95e..032567dfd6e2 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -13,7 +13,14 @@ #define REG_MEMC_CNTRLR_CONFIG 0x00 #define CNTRLR_CONFIG_LPDDR4_SHIFT 5 -#define CNTRLR_CONFIG_MASK 0xf +#define CNTRLR_CONFIG_MASK GENMASK(3, 0) +#define CNTRLR_CONFIG_SIZE_SHIFT 4 +#define CNTRLR_CONFIG_SIZE_MASK GENMASK(7, 4) +#define CNTRLR_CONFIG_WIDTH_SHIFT 8 +#define CNTRLR_CONFIG_WIDTH_MASK GENMASK(9, 8) +#define CNTRLR_CONFIG_TOT_WIDTH_SHIFT 10 +#define CNTRLR_CONFIG_TOT_WIDTH_MASK GENMASK(11, 10) +#define CNTRLR_CONFIG_RANK_SHIFT 16 #define REG_MEMC_SRPD_CFG_21 0x20 #define REG_MEMC_SRPD_CFG_20 0x34 #define REG_MEMC_SRPD_CFG_1x 0x3c @@ -63,6 +70,67 @@ static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc, return 0; } +static ssize_t ddr_rank_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", + memc->config_reg & CNTRLR_CONFIG_RANK_SHIFT ? + "dual" : "single"); +} + +static ssize_t ddr_size_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + u32 val = (memc->config_reg & CNTRLR_CONFIG_SIZE_MASK) >> + CNTRLR_CONFIG_SIZE_SHIFT; + + return sprintf(buf, "%dMb\n", 256 << val); +} + +static ssize_t ddr_total_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + u32 val = (memc->config_reg & CNTRLR_CONFIG_TOT_WIDTH_MASK) >> + CNTRLR_CONFIG_TOT_WIDTH_SHIFT; + + return sprintf(buf, "x%d\n", 8 << val); +} + +static ssize_t ddr_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + const char *ddr_type_to_str[] = { + "DDR2", + "DDR3", + "DDR4", + "GDDR5M", + "GDDR5", + "LPDDR4", + }; + u32 val = memc->config_reg & CNTRLR_CONFIG_MASK; + const char *type = "unknown"; + + if (val < ARRAY_SIZE(ddr_type_to_str)) + type = ddr_type_to_str[val]; + + return sprintf(buf, "%s\n", type); +} + +static ssize_t ddr_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct brcmstb_memc *memc = dev_get_drvdata(dev); + u32 val = (memc->config_reg & CNTRLR_CONFIG_WIDTH_MASK) >> + CNTRLR_CONFIG_WIDTH_SHIFT; + + return sprintf(buf, "x%d\n", 8 << val); +} + static ssize_t frequency_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -105,10 +173,20 @@ static ssize_t srpd_store(struct device *dev, struct device_attribute *attr, return count; } +static DEVICE_ATTR_RO(ddr_rank); +static DEVICE_ATTR_RO(ddr_size); +static DEVICE_ATTR_RO(ddr_total_width); +static DEVICE_ATTR_RO(ddr_type); +static DEVICE_ATTR_RO(ddr_width); static DEVICE_ATTR_RO(frequency); static DEVICE_ATTR_RW(srpd); static struct attribute *dev_attrs[] = { + &dev_attr_ddr_rank.attr, + &dev_attr_ddr_size.attr, + &dev_attr_ddr_total_width.attr, + &dev_attr_ddr_type.attr, + &dev_attr_ddr_width.attr, &dev_attr_frequency.attr, &dev_attr_srpd.attr, NULL, -- 2.34.1
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