Messages in this thread Patch in this message | | | From | Florian Fainelli <> | Subject | [PATCH 1/3] memory: brcmstb_memc: Cache configuration register value | Date | Fri, 24 Mar 2023 09:52:29 -0700 |
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The configuration register does not change once the DDR controller is configured, in preparation for providing more information about the DDR type/width in subsequent changes, store this value so we can retrieve it.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- drivers/memory/brcmstb_memc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/memory/brcmstb_memc.c b/drivers/memory/brcmstb_memc.c index 233a53f5bce1..67c75e21c95e 100644 --- a/drivers/memory/brcmstb_memc.c +++ b/drivers/memory/brcmstb_memc.c @@ -29,18 +29,15 @@ struct brcmstb_memc { struct device *dev; void __iomem *ddr_ctrl; unsigned int timeout_cycles; + u32 config_reg; u32 frequency; u32 srpd_offset; }; static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc) { - void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG; - u32 reg; - - reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK; - - return reg == CNTRLR_CONFIG_LPDDR4_SHIFT; + return (memc->config_reg & CNTRLR_CONFIG_MASK) == + CNTRLR_CONFIG_LPDDR4_SHIFT; } static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc, @@ -148,6 +145,9 @@ static int brcmstb_memc_probe(struct platform_device *pdev) of_property_read_u32(pdev->dev.of_node, "clock-frequency", &memc->frequency); + memc->config_reg = readl_relaxed(memc->ddr_ctrl + + REG_MEMC_CNTRLR_CONFIG); + ret = sysfs_create_group(&dev->kobj, &dev_attr_group); if (ret) return ret; -- 2.34.1
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