Messages in this thread Patch in this message | | | From | Elad Nachman <> | Subject | [PATCH v4 5/8] PCI: armada8k: support AC5 INTx PCIe interrupts | Date | Mon, 13 Mar 2023 14:40:13 +0200 |
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From: Elad Nachman <enachman@marvell.com>
Support message emulation of INTx PCIe interrupts for Marvell AC5/X. These message emulations require writing an additional status register with acknowledge bits.
Signed-off-by: Elad Nachman <enachman@marvell.com> --- v4: Split the part not handling INTx interrupts to a separate patch
drivers/pci/controller/dwc/pcie-armada8k.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 02481ecadd25..2b94e32853ad 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -61,6 +61,7 @@ struct armada8k_pcie_of_data { #define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C) #define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20) +#define PCIE_GLOBAL_INT_CAUSE2_REG (PCIE_VENDOR_REGS_OFFSET + 0x24) #define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28) #define PCIE_INT_A_ASSERT_MASK BIT(9) #define PCIE_INT_B_ASSERT_MASK BIT(10) @@ -267,8 +268,14 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) */ val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); - if ((PCIE_MSI_MASK_AC5 & val) && (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5)) - dw_handle_msi_irq(&pci->pp); + if (pcie->pcie_type == ARMADA8K_PCIE_TYPE_AC5) { + if (PCIE_MSI_MASK_AC5 & val) + dw_handle_msi_irq(&pci->pp); + + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG); + /* Now clear the second interrupt cause. */ + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG, val); + } return IRQ_HANDLED; } -- 2.17.1
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