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    SubjectRe: [PATCH v4 4/8] dt-bindings: PCI: dwc: Add dma-ranges, region mask
    On Mon, Mar 13, 2023 at 02:40:12PM +0200, Elad Nachman wrote:
    > From: Elad Nachman <enachman@marvell.com>
    >
    > Add properties to support configurable DMA mask bits and region mask bits:
    >
    > 1. configurable dma-ranges is needed for Marvell AC5/AC5X SOCs which
    > have their physical DDR memory start at address 0x2_0000_0000.
    >
    > 2. Configurable region mask bits is needed for the Marvell Armada
    > 7020/7040/8040 SOCs when the DT file places the PCIe window above the 4GB region.
    > The Synopsis Designware PCIe IP in these SOCs is too old to specify the
    > highest memory location supported by the PCIe, but practically supports
    > such locations. Allow these locations to be specified in the DT file.
    >
    > Signed-off-by: Elad Nachman <enachman@marvell.com>
    > ---
    > v4:
    > 1) Fix commit message and its formatting
    >
    > 2) Replace num-dmamask with dma-ranges
    >
    > .../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 5 +++++
    > Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 6 ++++++
    > 2 files changed, 11 insertions(+)
    >
    > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
    > index d87e13496834..3cb9af1aefeb 100644
    > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
    > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
    > @@ -261,6 +261,11 @@ properties:
    >
    > dma-coherent: true
    >
    > + num-regionmask:
    > + description: |
    > + number of region limit mask bits to use, if different than default 32
    > + maximum: 64

    This should be implied from the compatible string.

    > +
    > additionalProperties: true
    >
    > ...
    > diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
    > index 1a83f0f65f19..ed7ae2a14804 100644
    > --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
    > +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
    > @@ -197,6 +197,12 @@ properties:
    > - contains:
    > const: msi
    >
    > + dma-ranges:
    > + description:
    > + Defines the DMA mask for devices which due to non-standard HW address
    > + assignment have their RAM starting address above the lower 32-bit region.
    > + Since this is a mask, only the size attribute of the dma-ranges is used.
    > +

    No need for this, it is already defined in pci-bus.yaml.

    The description is wrong here anyways. The purpose is to translate
    inbound PCI addresses to parent bus addresses (and eventually CPU
    addresses).

    Rob

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